The present invention relates to a co-processor system having a main processor and co-processors which add to the main processor dedicated functions suitable for various applications. More particularly, the invention relates to a data transfer control method and apparatus for a co-processor system wherein a data processing co-processor which requires frequent read/write relative to an external memory can efficiently access the memory.
One example of conventional methods of transferring data between a co-processor and a memory is described in the document regarding a numerical operation processor 8087 of Intel, U.S.A. (Intel, Microprocessor and Peripheral Handbook Volume I-Microprocessor, 230843-004, pp. 2-122 to pp. 2-143). In this case, when a main processor executes an input/output instruction for a co-processor, the main processor first calculates an address value of the memory and outputs it. After storing the address value as a start address of memory data, the co-processor activates a memory access control circuit included therein to access the memory for necessary words starting from the start address.
Another example is described in a document regarding a microprocessor MC68020 of Motorola, U.S.A. (Motorola, MC68020 32-Bit Microprocessor User's Manual, pp. 8-1 to pp. 8-7).
In this method, for transfer of control information on a co-processor, the main processor reads/writes a transceiver register for transmission/reception relative to the co-processor. In accessing memory data, the co-processor requests a memory read/write from the main processor which in turn performs a memory read/write either by writing data read out from the memory into the transceiver register or by writing data read out from the transceiver register into the memory.
With the former method of the above-described prior art, it is necessary for the co-processor to have therein a memory access control circuit such as a Direct Memory Access Controller (DMAC), resulting in a possible increase in cost and development processes. With the latter method, it is necessary for the main processor to repeat read/write relative to the memory and the transceiver register of the co-processor, thus posing a problem of degrading a data transfer efficiency.